get_ip_core
Fetch manifest and HDL source for a core
How to use it
get_ip_core is exposed by the FpgaZeroMCP MCP server. Add the server to your MCP client (Claude Desktop, Cursor, Windsurf and others), and the get_ip_core tool becomes available to the model automatically. See the full listing for setup details and every tool this server provides.
Install FpgaZeroMCP
python /path/to/fpgaZeroMCP/server.pyOther tools in FpgaZeroMCP (25)
Check progress — status, elapsed time, parsed phase/utilization/timing
Kill a running background build
Report which OSS CAD Suite tools are installed, with paths and versions
Delete old build logs by age and total size
Auto-format via verible-verilog-format (V/SV) or vsg (VHDL)
Get a parameterized instantiation snippet + source files
Structured per-line diagnostics — Verilator → verible fallback (V/SV), GHDL (VHDL)
Import a local FuseSoC CAPI2 .core file
Download a GitHub repo into the local registry
Syntax/error check via iverilog (V/SV) or GHDL (VHDL) — single file
Lint multiple files together so cross-module references resolve
Enumerate built-in board presets (target/device/package/clock)
List all tracked builds (running and finished)
Browse the local registry, filter by category
Run a LiteX board target with --build
Run a LiteX board target with fully custom args
Generate a LiteX SoC without building gateware
Yosys + nextpnr in one step. Board presets, constraint auto-detection, bitstream written to disk (bitstreampath)
Flash a bitstream via iceprog or openFPGALoader
Re-scan core directories without restarting the server
Search GitHub for MIT-licensed FPGA IP repos
Compile and run testbenches — iverilog (V/SV) or GHDL (VHDL). Accepts code, files, or projectdir. Returns verdict + VCD summary
Start a long-running command in the background (allowlisted EDA tools only)
Yosys synthesis with resource stats. Accepts code, files, or projectdir. Verilog, SV, VHDL