FpgaZeroMCP
未认领An open-source Model Context Protocol server that gives AI assistants a complete FPGA toolchain — lint, simulate, synthesize, place-and-route, and a live IP core registry backed by GitHub.
安装
python /path/to/fpgaZeroMCP/server.py更多AI & ML服务器
浏览完整目录安全概况
已认领和已认证的服务器每周接受一次静态扫描，显示代码能触及的范围（外部服务、环境变量、shell 命令、代理配置目录）以及带有已知公告的依赖。认领此列表即可获得。 安全概况的工作原理
26 个工具中显示 26 个
文档中列出的工具 (26)
内容来自项目文档。服务器握手不会验证每个工具的说明或行为。
build_status
Check progress — status, elapsed time, parsed phase/utilization/timing
cancel_build
Kill a running background build
check_tools
Report which OSS CAD Suite tools are installed, with paths and versions
cleanup_build_logs
Delete old build logs by age and total size
format_hdl
Auto-format via verible-verilog-format (V/SV) or vsg (VHDL)
generate_ip
Get a parameterized instantiation snippet + source files
get_diagnostics
Structured per-line diagnostics — Verilator → verible fallback (V/SV), GHDL (VHDL)
get_ip_core
Fetch manifest and HDL source for a core
import_fusesoc_core
Import a local FuseSoC CAPI2 .core file
import_github_core
Download a GitHub repo into the local registry
lint_hdl
Syntax/error check via iverilog (V/SV) or GHDL (VHDL) — single file
lint_project
Lint multiple files together so cross-module references resolve
list_boards
Enumerate built-in board presets (target/device/package/clock)
list_builds
List all tracked builds (running and finished)
list_ip_cores
Browse the local registry, filter by category
LiteX
litex_build
Run a LiteX board target with --build
litex_flow
Run a LiteX board target with fully custom args
litex_soc
Generate a LiteX SoC without building gateware
place_and_route
Yosys + nextpnr in one step. Board presets, constraint auto-detection, bitstream written to disk (bitstreampath)
program_fpga
Flash a bitstream via iceprog or openFPGALoader
reload_registry
Re-scan core directories without restarting the server
search_github_cores
Search GitHub for MIT-licensed FPGA IP repos
simulate
Compile and run testbenches — iverilog (V/SV) or GHDL (VHDL). Accepts code, files, or projectdir. Returns verdict + VCD summary
start_build
Start a long-running command in the background (allowlisted EDA tools only)
synthesize
Yosys synthesis with resource stats. Accepts code, files, or projectdir. Verilog, SV, VHDL